1. Field of the Invention
The present invention relates to a method and a circuit for providing a horizontal scan or line scan control signal of a TV set.
2. Discussion of the Related Art
FIG. 1 schematically shows the general architecture of a circuit for providing signals for controlling the vertical and horizontal scanning of a TV set.
FIGS. 2 and 3 show signals characteristic of the circuit of FIG. 1.
Generally, and neglecting carrier frequencies, a TV set receives a composite video signal CVBS which comprises a frame signal 4 comprised of video signals 5, each corresponding to the information to be displayed on a line of the TV screen, separated by horizontal synchronization (or line synchronization) pulses 6. Between two frame signals 4, composite video signal CVBS comprises an area only containing synchronization signals which divide into so-called frame pre-synchronization signals 7, so-called frame synchronization signals 8, so-called frame post-synchronization signals 9, and so-called horizontal synchronization setting signals 10.
Composite video signal CVBS is provided to a separation unit 11 (SYNC. SEPARATOR) which provides a horizontal and vertical synchronization signal SVHS. Unless otherwise mentioned, the signals considered hereafter will be substantially binary signals having a high state and a reference state, respectively designated as 1 and 0 hereafter. Some specific binary signals may vary between a low state, designated as −1, and the high state. Signal SVHS substantially corresponds to inverted composite video signal CVBS without video signals 5. Signal SVHS ensures the vertical and horizontal synchronization of the TV screen scanning. Signal SVHS is transmitted to a vertical synchronization separation unit 12 (VERTICAL SEPARATOR) which provides a vertical synchronization signal SVS equal to 1 over the entire duration of frame synchronization signals 8 of the CVBS signal and equal to 0 otherwise. Signal SVS is transmitted to a signal provision unit 14 (VERTICAL SIGNALS UNIT) adapted to generating, from SVS, a vertical screen scan control signal and a horizontal synchronization inhibition signal SFRI transmitted to the input of an inverter 16 having its output connected to an input of a logic AND gate 18. Signal SFRI is at 1 over the entire duration of frame synchronization signals 8 and of frame post-synchronization signals 9, and at 0 otherwise. The other input of logic gate 18 receives synchronization signal SVHS. Logic gate 18 provides a horizontal synchronization signal SHS transmitted to a phase-locked loop 20 and equal to 0 when SFRI is at 0 and equal to signal SVHS otherwise. Signal SFRI is used to deactivate loop 20 during the return of the vertical screen scanning before the beginning of the display of a new frame.
Phase-locked loop 20 comprises a phase comparator 22 receiving as an input horizontal synchronization signal SHS and a signal PH with a ½ duty cycle. Phase comparator 22 compares signals SHS and PH and provides a loop current IPLL to a capacitor 24. Voltage SC across capacitor 24 is applied to the input of a voltage-controlled oscillator 26 (VCO). Voltage-controlled oscillator 26 generates a periodic oscillation signal SO with a ½ duty cycle equal to 1 or −1, the frequency of which depends on control signal SC. Signal SO is provided to a frequency divider 28 (/) and to a signal provision unit 30 (HORIZONTAL SIGNALS UNIT). Frequency divider 28 provides signal PH which is equal in frequency to signal SHS when phase-locked loop 20 is locked. Signal generator 30 especially generates signals SHS for controlling the horizontal screen scanning.
In FIG. 3, horizontal synchronization signal SHS is represented at an enlarged scale with respect to FIG. 2. The phase comparator compares signals PH and SHS to provide current IPLL equal to a value +I when signals PH and SHS are both at 1, to a value −I when signal SHS is at 1 and signal PH is at −1, and equal to 0 when signal SHS is at 0. In normal operation, the frequencies of signals SHS and PH are identical and the falling edges of PH occur in the middle of the synchronization pulses of SHS. Current IPLL successively switches from 0 to +I when signal PH is at 1 and signal SHS switches from 0 to 1, to −I when signal SHS is at 1 and signal PH switches to −1, then again to 0 when signal SHS switches to 0. When current IPLL is at +I or at −I, voltage SC across capacitor 24 respectively corresponds to an ascending ramp 32 or a descending ramp 34. When current IPLL switches from −I to 0, voltage SC keeps the value acquired at the end of descending ramp 34.
In normal operation, ascending ramp 32 and descending ramp 34 of control signal SC are symmetrical. Control signal SC then keeps a substantially constant value before and after a pulse of horizontal synchronization signal SHS. The frequency of oscillating signal SO thus is substantially constant. When the frequency or the phase of signal SHS varies, ramps 32, 34 are no longer symmetrical so that the average value of signal SC varies to adapt the frequency and the phase of signal PH.
Currently, to prevent the copying of the composite video signal, for example, on a video tape, parasitic pulses are added between two pulses of the horizontal synchronization signal on a portion of composite video signal CVBS. Generally, parasitic pulses are only added at the level of the signal for setting the horizontal synchronization 10, that is, for example, from the fifth to the twenty-first line, before the beginning of a frame signal.
FIG. 4 shows an example of a possible shape of horizontal synchronization signal SHS comprising horizontal synchronization pulses 39 and parasitic pulses 40. The number, the position, and the width of parasitic pulses 40 between two synchronization pulses 39 may be variable.
Parasitic pulses 40 tend to disturb the operation of phase-locked loop 20 by varying the frequency of oscillating signal SO from which the signals controlling horizontal screen scanning signals SLS are generated.
When parasitic pulses 40 are no longer present, phase-locked loop 20 tends to recover the frequency and the phase of horizontal synchronization pulses 39. However, due to the time constant of loop 20, the recovery may extend over several lines. The first video signals 5 displayed on the screen may then be offset with respect to the vertical left-hand edge of the screen.
To solve such a disadvantage, there is a tendency to temporarily increasing the time constant of the phase locked-loop as long as parasitic pulses 40 are present, to limit the frequency variations of signal So, then to return to a normal time constant when parasitic pulses 40 are no longer present. However, in this case also, the phase-locked loop may not recover sufficiently fast the frequency and phase of horizontal synchronization pulses 39. The first lines displayed on screen may then be shifted with respect to the vertical left-hand edge of the screen.